1. Field
Exemplary embodiments of the present invention relate to a memory device and a method for verifying the same.
2. Description of the Related Art
A nonvolatile memory is a memory device, which maintains data stored therein, even though power supply is cut off. The nonvolatile memory stores data by using such a property that a threshold voltage of a memory cell is shifted by controlling the amount of charge maintained in a conductive band of a floating gate.
When a program pulse is applied to a floating gate, the threshold voltage of a memory cell rises. Depending on the value of data, which is to be stored in a memory cell using the program pulse, the threshold voltage of the memory cell may differ. However, because a plurality of memory cells in a nonvolatile memory have different characteristics, the threshold voltages of memory cells that stores the same data may not have one value, but form a regular distribution.
Meanwhile, the nonvolatile memory may store one-bit data or multi-bit data in one memory cell. In general, a memory cell that stores one-bit data is referred to as a single level cell (SLC), and a memory cell that stores multi-bit data is referred to as a multi level cell (MLC). The SLC has an erase state and a program state depending on a threshold voltage. The MLC has an erase state and a plurality of program states depending on a threshold voltage.
FIG. 1 is a diagram for illustrating distributions of threshold voltages of MLCs capable of storing two-bit data.
Referring to FIG. 1, the threshold voltages of memory cells differ based on the program states of the memory cells. The threshold voltages of memory cells in an erase state ERA are lower than a first voltage PV1. The threshold voltages of memory cells in a first program state PG1 are higher than the first voltage PV1 and lower than a second voltage PV2. The threshold voltages of memory cells in a second program state PG2 are higher than the second voltage PV2 and lower than a third voltage PV3. The threshold voltages of memory cells in a third program state PG3 are higher than the third voltage PV3. Here, the erase state ERA and the first to third program states PG1 to PG3 indicate that data that have different values are stored in memory cells.
Here, the first to third voltages PV1 to PV3 serve as reference voltages for indicating a state for a memory cell among the possible states that include erase state ERA and first to third program states PG1 to 3. Therefore, when verifying whether or not a memory cell was normally programmed or reading data of a memory cell, the first to third voltages PV1 to PV3 are used.
The verification operation will be described in more detail as follows. When a program operation for a memory cell is performed, a program pulse is applied to a word line corresponding to the memory cell to be programmed, and a verification voltage is then supplied to the word line corresponding to the memory cell to be programmed, in order to verify whether the memory cell is normally programmed or not. The first to third voltages PV1 to PV3 may be used as the verification voltage. As a result of the verification operation, when the memory cell is not normally programmed, a program pulse is further applied to the memory cell, and when the memory cell is normally programmed, the program operation for the memory cell is completed.
MLCs have a plurality of threshold voltage distributions. Therefore, to secure a sufficient read margin when performing a read operation in the respective states ERA and PG1 to PG3, the widths of the threshold voltage distributions based on the respective states need to be reduced. Hereafter, a double verification program for reducing the widths of threshold voltage distributions will be described with reference to FIG. 2.
FIG. 2 is a diagram explaining the double verification program. FIG. 2 illustrates a case where a memory cell is programmed into the first program state PG1 of FIG. 1.
In the case of a general program operation, a verification operation is performed using only the first voltage PV1 as a verification voltage to check whether the memory cell was programmed into the first program state PG1 or not. In the case of a double verification program operation, the threshold voltage of the memory cell is verified one more time by using a first sub voltage DPV1, which is lower than the first voltage PV1, as a sub verification voltage.
The double verification program will be described in more detail as follows. First, a program pulse is applied to a word line that corresponds to a memory cell in an erase state ERA, which is to be programmed. After the program pulse is applied, the first sub voltage DPV1 is used to verify whether the threshold voltage of the memory cell is higher than the first sub voltage DPV1 or not, and the first voltage PV1 is then used to verify whether the threshold voltage of the memory cell is higher than the first voltage PV1 or not. Hereafter, to distinguish a state where program is completed from a state where program is not completed but the threshold voltage of a memory cell is programmed at the first sub voltage DPV1 or more, the former is referred to as a target program state, and the latter is referred to as a sub program state.
For a memory cell that has a lower threshold voltage than the first sub voltage DPV1 as the verification result, a program pulse is applied under the same condition as the previous condition. Furthermore, for a memory cell that has a threshold voltage higher than the first sub voltage DPV1 and lower than the first voltage PV1, that is, a memory cell in the sub program state, the voltage of a bit line is increased, and a program pulse is then applied. For a memory cell that has a higher threshold voltage than the first voltage PV1, that is, a memory cell in the target program state, an inhibit voltage is supplied to the bit line, and a program pulse is then applied.
Similarly, even when a memory cell is programmed into the second program state PG2, a second sub voltage, which is lower than the second voltage PV2 and higher than the first voltage PV1, is used to verify the memory cell two times. However, because the third program state PG3 is located in the rightmost side, the width of the threshold voltage distribution does not need to be reduced. Thus, the double verification program may be not required in the case of the third program state.
In general, when a program pulse is applied, the change in threshold voltage of a memory cell is reduced with the increase in voltage of a bit line. Therefore, in the case of a memory cell that has a threshold voltage, which does not correspond to the sub program state and the target program state, the threshold voltage of the memory cell is significantly changed when a program pulse is applied. In the case of a memory cell in the sub program state, the threshold voltage of the memory cell is changed when a program pulse is applied, but changed less than that of a memory cell in the erase state. In the case of a memory cell in the program state, the threshold voltage of the memory cell is not almost changed even though a program pulse is applied. Therefore, it is possible to reduce the width of the threshold voltage distribution of memory cells in the first program state PG1. In the case of the double verification program, however, two voltages are used to verify whether a memory cell is programmed on program state. Therefore, a time required for performing the verification operation is significantly increased.